Gate-all-around (or GAA) nanowire devices are a promising candidate for complementary metal oxide semiconductor (CMOS) device scaling. Some GAA nanowire device designs form the gate electrode around a freely suspended wire(s). In that case, each freely suspended wire requires tethering, anchor or landing pad structures.
For silicon-on-insulator (SOI) nanowires this can be formed by making a landing pad of continuous SOI adjacent to a grouping of nanowires. Thus, multiple nanowires can share the same landing pads wherein, for example, the nanowires and pads are arranged in a ladder-like configuration with the pads attached at opposite ends of the nanowires and where the nanowires look like the rungs of a ladder. Multiple gates are often then patterned over the set of nanowires and landing pads in a given active area of a wafer.
Thus when planning devices having freely suspended wires, designers must include landing pads in the design. However, the specifications of the various devices in the design oftentimes vary from one device to another. For instance, variations in the nanowire length are common as well as the number of nanowires in parallel for a given device or set of devices. Accordingly, the placement and size of the landing pads will also vary.
Based on this device variation, manually placing each of the landing pads in the correct location in the design can be an extremely time-consuming process. Thus, techniques for automating the landing pad design process based on data about the device would be desirable.